The invention relates to calibrating timing on a tester that tests integrated circuits. More specifically, the invention relates to compensating for the effects of round-trip delay on signals transmitted between the automatic test equipment and a device under test.
Current integrated circuit (IC) technologies continue to increase device speeds, requiring manufacturing process changes, adjustments, and modifications to accommodate the build and testing of the ICs. For example, faster test cycles and higher accuracy in the implementation and design of automated test equipment (ATE) are necessary to communicate with and perform in-situ testing of these high speed ICs.
Automated test equipment is used to simulate the operating conditions that an integrated circuit will experience when used in an application. An integrated circuit undergoing testing is known as a device under test (DUT). Generally, the ATE is controlled by a computer, which executes a set of instructions, generally software programmable instructions. The ATE presents the correct voltages, currents, timings, and functional states to the DUT and monitors the response from the DUT for each test applied. The ATE then compares the result of each test to pre-defined limits and a pass/fail decision is made. In a conventional test configuration, pin electronics apply test signals to nodes of the DUT, detect output signals produced by the DUT in response to applied test signals, and compare the detected output signals with expected values at times dictated by the timing edges provided by a timing generator.
One of the responsibilities of the ATE is to calibrate signal timing. Timing calibration corrects for time delays in routing a signal from the tester to a DUT, or conversely, from the DUT to the tester, or both, due to constraints present in the testing equipment. These timing delays are due to, in part, several layers of interconnections between the DUT and the tester. The round-trip delays significantly limit the programming flexibility of a tester, especially when testing high-speed electronic circuitry. Manual techniques to eliminate or reduce these delays are complex, time consuming, and error prone. The present invention reduces the complexity and eliminates errors induced by current testing techniques.
Adjustments for signal delays to the tester wiring are commonly made in ATE using a technique known as time domain reflectometry (TDR). Time domain reflectometry is a well-known technique for testing lines, in which, for example, one or more electrical test pulses are transmitted into a line at one end, and the voltage on the line at the same end is measured as a function of time after transmission of the test pulse. Any impedance mismatch in the line caused by a fault, for example, will cause a reflection of the test pulse to be detected at a time after transmission of the test pulse that corresponds to the position of the impedance mismatch along the line. TDR is used to detect discontinuities in the impedance of a cable or signal line, as well as the specific location of each discontinuity. The magnitude of each discontinuity is proportional to the applied signal. The impedance of a discontinuity is a function of transducer voltage. Adjustments to the ATE are then made depending upon the TDR measurements. The adjustments address the delays through pin driver electronics and pin receiver electronics, device test interface boards, and sockets. This adjustment of time for signal travel, while improving signal placement at the DUT, can actually induce errors if one does not factor in other significant variables, such as the proximity and types of the programmed signal edges and the TDR adjustment value.
FIG. 1 depicts a circuit diagram of a typical prior art tester circuit 10. A channel driver 12 receives drive data and sends a test signal to the DUT (not shown) through pin electronics, a device interface board wire 14, and a device socket 16. These interfaces impart time delays in the signal as the signal traverses through their length. A channel receiver circuit 18 receives the return test signal and DUT response signal, and compares the response to expected values. Time delays, Tpe, Tdib, and Ts are associated with the time delay through the pin electronics, device interface board, and the socket, respectively. The signal delay equation is represented by the sum of the individual time delays:Tdelay=Tpe+Tdib+Ts 
This equation assumes that the pin electronics time delay, Tpe, is approximately the same for both the driver and the receiver. If one desires a signal transition edge to occur at the DUT at Tdesired, the tester must adjust the test time by moving the signal edge to emit from the channel driver circuit 12 earlier by an amount Tdelay. Thus, the signal is transmitted out of the channel driver 12 at a time:Tdriver=Tdesired−Tdelay 
Timing the signal for transmission at Tdriver places the edge of the transition signal at the DUT at Tdesired. FIG. 2 depicts the input waveform at the channel driver, showing the delay in signal transmission.
Similarly, to adjust for the delay on the tester's measure and receive circuitry, which measures the signal coming out of the DUT, one needs to adjust for the signal propagation in the other direction. The delay effects on the waveform received for comparison is depicted in FIG. 3. The measured time at the comparator, Tmeasure, adds to the transmission delay time, Tdelay, to obtain the received time delay, Treceive:Treceive=Tmeasure+Tdelay 
However, a situation exists on device pins that are utilized as bidirectional. In this case, the tester needs to both apply a signal and measure a response on the same device pin. When the device data and test requirements cause a set of adjacent device cycles, where the tester transitions from measuring the device response to applying a signal, referred to as an output-to-input turnaround, the self-adjusting feature of the tester moves each signal edge to cause the tester to measure its own drive waveform. A problem occurs when the tester attempts to null out the inherent delay in the signal propagation time from the pin electronic circuitry to the DUT, and vice-versa.
The drive waveform edge occurs at Tdriver=Tdesired Tdelay, and the receive edge occurs at Treceive=Tmeasure+Tdelay. When the difference between Tmeasure and Treceive become less than Tdelay, the tester comparator circuit is actually measuring the tester drive circuit. FIG. 4 depicts the combined effects of TDR delay adjustments on waveforms. The signal overlap 40 due to autocorrection is shown for the difference in the measured cycle and the applied cycle. To eliminate this problem, the current state of the art has focused on reducing the delays from the channel pin electronics to the DUT, which has shown to be a costly endeavor.
Additionally, manual means have been used to adjust for errors induced by the self-correcting algorithms in the tester hardware and software. However, the complexities to the end user increase, and errors are frequently induced under these approaches. One such means is to program two adjacent channels in separate modes, one as an input and one as an output. All the waveforms and test data are then programmed to generate the appropriate waveforms and apply the appropriate data on each channel. This technique requires twice as many waveforms and twice as much data to program, taking up time and tester resources.
Another technique for eliminating this problem at the tester is for ATE to be developed with restrictions on the timing edge placement, especially for output-to-input cycles. This is commonly addressed by inserting a so-called dummy cycle. Effectively, a dummy cycle allows for the delays to catch up. The dummy cycle solves tester-induced error; however, it does not test the device under actual operating conditions.
The present invention details an apparatus and method, to be implemented by the ATE manufacturer, supplier, or other technician, which solves this round trip delay issue, and makes the tester channels appear as another mode that the end user can program using current programming techniques. In the preferred embodiment, this methodology is implemented in an ATE compiler.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method and apparatus to compensate for the effects of round-trip delay on signals transmitted between automatic test equipment and a device under test.
It is another object of the present invention to provide a method and apparatus to test and compensate for pins of a device under test that are utilized as bidirectional.
A further object of the invention is to provide a method and apparatus to allow an automatic test equipment tester to null out the inherent delay in signal propagation time from pin electronic circuitry to the device under test.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.